In interactive behavioral synthesis, the designer can control the design process at every stage, including modifying the schedule of the design to improve its performance. In this report, we present a methodology for performance optimization in interactive behavioral synthesis. Also proposed in this report are several quality metrics and hints that can assist the user in utilizing the proposed methodology. When the user is optimizing the performance of the design, one important decision is the selection of a clock period. We have developed an algorihm to estimate the effect of different clock periods on the execution time of the design. This algorithm can be used to facilitate clock period selection by the user in order to optimize the perf...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
Due to recent increases in chip complexity, behavioral synthesis has become an important area of res...
When synthesizing a hardware implementation from behavioral descriptions, an important decision is t...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...
Clock selection has a significant impact on the performance and quality of designs in high-level syn...
This paper analyzes the effect of resource sharing and assignment on the clock period of the synthes...
Abstract. The performance of real world applications often critically depends on a few computational...
Multicycle scheduling, i.e., the possibility to schedule operations over several clock cycles, gives...
Heuristics are widely used for solving computational intractable synthesis problems. However, until ...
Eliminating timing violations using clock tree optimization (CTO) persist to be a tedious problem in...
ISBN: 0769506461Introducing testability considerations as soon as possible in the design process res...
This paper describes a technique to integrate the three major tasks of high-level synthesis (schedul...
In this paper, we describe a timing model for clock estimation during high-level synthesis. In order...
Due to the ad-hoc specication methodology, typical ASIC de-signs are highly unbalanced with respect ...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
Due to recent increases in chip complexity, behavioral synthesis has become an important area of res...
When synthesizing a hardware implementation from behavioral descriptions, an important decision is t...
Early scheduling algorithms usually adjusted the clock cycle duration to the execution time of the s...
Clock selection has a significant impact on the performance and quality of designs in high-level syn...
This paper analyzes the effect of resource sharing and assignment on the clock period of the synthes...
Abstract. The performance of real world applications often critically depends on a few computational...
Multicycle scheduling, i.e., the possibility to schedule operations over several clock cycles, gives...
Heuristics are widely used for solving computational intractable synthesis problems. However, until ...
Eliminating timing violations using clock tree optimization (CTO) persist to be a tedious problem in...
ISBN: 0769506461Introducing testability considerations as soon as possible in the design process res...
This paper describes a technique to integrate the three major tasks of high-level synthesis (schedul...
In this paper, we describe a timing model for clock estimation during high-level synthesis. In order...
Due to the ad-hoc specication methodology, typical ASIC de-signs are highly unbalanced with respect ...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
Due to recent increases in chip complexity, behavioral synthesis has become an important area of res...