Optimal Clock Period for Synthesized Data Paths

The choice of a clock period in designs with multicycle operations have a major influence on operator allocation as well as execution time. For technologies with signi cant inter-connection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. First a bound ow graph is constructed by reflecting the allocation and binding information on the data ow graph. All potentially critical paths in this bound ow graph are identified. Execution time is computed by evaluating these path lengths and thus avoiding rescheduling. Based on execution times, a set of potentially optimal clock periods is chosen. An optimal clock period is one which results in the minimum execution time while meeting a controller cost constraint. Finally, the controller costs at these clock periods along with the execution times decide the optimal clock period. Extensive experimental results on data paths synthesized from high-level synthesis bench-marks establish both the utilityaswell as the efficiency of our approach. These results clearl