Performance and Area Optimization using Sequential Flexibility

Due to the ad-hoc specication methodology, typical ASIC de-signs are highly unbalanced with respect to the timing criticality of their logic paths. Traditional combinational synthesis does not support borrowing of timing slack across registers and therefore may result in a drastic overdesign of many paths and an overall loss of performance. This can be particularly harmful when paths are sped up through resizing which incurs an exponential cost in area. In this paper we present how clock latency scheduling inter-leaved with combinational optimization can be applied to optimize the performance and area of designs. In contrast to a retiming-based approach, we show that clock latency scheduling is compu-tationally more efcient for inclusion in an inner synthesis loop and can also perform slack balancing which provides a good starting point for heuristic area minimization. Our preliminary experiments applying the presented ow based on an industrial synthesis tool to standard benchmark circuits and customer ASIC designs show an average improvement in performance of 17 % and in area of 2%.