Extended HLS with high-level descriptive language for configurable algorithm-level spatial structure design

High-level synthesis (HLS) tools have greatly improved the development efficiency of FPGA accelerators in many application areas. With the HLS tools, FPGA designers can focus more on algorithm specifications using software languages such as C/C++, OpenCL, and Python. However, due to the fact that CPU-oriented software languages are designed to describe sequential execution, the repurposing of these languages yields insufficient support for describing parallel data execution and flexible spatial structures on FPGA architecture. To strengthen HLS’s ability to describe configurable algorithm-level spatial structures, we propose fusing hardware-friendly design patterns, namely high-level descriptive language, into imperative programming model on Python. By learning advantages from hardware description language (HDL) and utilizing the HLS scheduling engine to extract instruction-level parallelism, our newly proposed model can help designers finely and flexibly describe the parallelism at the loop level and the kernel level, as well as spatial structures of storage elements.U of I OnlyUndergraduate senior thesis not recommended for open acces