Evaluation of high-level languages for general FPGA acceleration

High-Level Synthesis (HLS) improves productivity compared to Register-Transfer Level (RTL) hardware descriptions. Despite its rise in popularity, there is still a performance gap compared to RTL design flows. One promising approach to bridge this gap has been the use of Domain-Specific Languages (DSLs), which allow increasing performance by restricting the application domain. In recent years, two promising DSL-based HLS tools have been proposed, Spatial and HeteroCL, that aim to translate these benefits into the design of general accelerators. In this work we compare these tools with custom RTL designs over diverse benchmarks, showing that a reduction of, on average, 10x of lines of code comes with a performance gap that can be as low as 8%. Our main conclusion is that the tools are suitable for faster design flows, and that previous hardware development experience and algorithm properties should be the main deciding factors between both similar tools