Partial Evaluation Based Triple Modular Redundancy For Single Event Upset Mitigation

We present a design technique, called partial evaluation triple modular redundancy for hardening combinational circuits against Single Event Upsets (SEU). The input environment is given in terms of signal probabilities of the lines. This is useful information to determine the redundant gates of the given circuit. The basic ideas of partial redundancy and temporal triple modular redundancy are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. This technique fails in cases when the actual inputs to the circuit are not in accordance to the rounded logic values. In such cases the technique of temporal TMR is used. However, there is some overhead in this process because of the voter circuits and the need to choose the outputs computed by partially evaluated circuit and circuit using temporal TMR. For testing the circuit exhaustively against SEUs, a fault insertion simulator is used. This simulator introduces errors in the circuits during simulation which represent SEUs. This technique of partial evaluation redundancy is thoroughly tested on MCNC’91 benchmarks using Cadence NCLaunch simulator. By employing this technique, in most of the cases we can reduce the area overhead of the hardened circuit when compared with the traditional Triple Modular Redundancy (TMR). The improvement in area is based on the total number of gates and the actual number of outputs. For circuits with large number of gates and less number of outputs, there is greater savings in area. In some cases, the area overhead because of the proposed technique is greater than the traditional TMR. This usually occurs in smaller circuits or in circuits with more number of outputs