A Framework for Estimating Vulnerability of Digital Circuits against Single Event Multiple Transients

Recent deep-submicron-technology-based integrated circuits (ICs) are substantially more susceptible to transient faults. Thus, the soft errors that occurred due to transient faults are more important than they have ever been. As a result, it is critical to identify any functional inconsistencies and component failures as early in the design process as possible in order to avoid potentially threatening events. Early stage analysis of the integrated circuits enables designers to build fault tolerant systems by applying some fault-mitigation techniques. Existing methodologies for investigating single event transients (SETs) or single event multiple transients (SEMTs) faults often lack the ability to perform system analysis due to the state-explosion (such as simulation-based testing) or due to the ignoring of post-layout information (such as netlist-based analysis). In this thesis work, we develop a methodology to model and analyze the effect of transient faults at higher-level of abstraction. In the proposed methodology, we include the effect of SEMT on the integrated circuit (IC) device by considering its post-layout information. It also includes checking SEMT propagation throughout the circuit and the effect of all three masking factors (e.g. logical masking, electrical masking, and latching-window effect). The methodology also provides insights into design vulnerabilities and critical areas of the IC layout. It is further extended to estimate the vulnerabilities of registers in openMSP430 core while running a specific application