Hardened by design approaches for mitigating transient faults in memory-based systems

In radioactive environments, particle strikes can induce transient errors in integrated circuits (ICs). Strikes directly disrupting memory are known as Single-Event Upsets (SEUs), while strikes initially disrupting logic are called Single-Event Transients (SETs). Chips manufactured in aggressive technologies may also experience Multiple-Bit Upsets (MBUs). This research focuses on novel hardened by design circuit-level approaches to protecting integrated circuits against SEUs, SETs and MBUs. A number of system-level designs have been developed utilizing these approaches to demonstrate their capabilities. Many of the design-hardened memory circuits considered in this study share a common theme, which is the ability to bypass transient faults. This is critical for performance, as it allows a system to proceed with subsequent operations while recovering from a disruption. Among the considered approaches, the novel Triple Path DICE (TPDICE) structure is the most balanced. This structure requires only two of its three inputs to be resolved during a write operation to ensure recovery. The recovery process requires approximately 50-100ps in 0.18 m CMOS