Efficacious Redundancy Technique for Enriched Lockstep Architecture

Abstract- Fault tolerance system plays a prominent role in many digital systems. A new intensifying lockstep scheme is proposed and implemented in EDA VLSI tool, which can mitigate Single-Event Upsets (SEU). Faults are detected and eliminated without interrupting the normal functioning of the circuit. Single point of failure, is eliminated and implemented as a fault tolerant using a Triple Modular Redundancy (TMR). This technique incorporates both transient and permanent faults. The new intensifying lockstep scheme requires significantly shorter recovery time than conventional lock step. It uses significantly less number of slices. Conventional lockstep scheme uses duplication with comparison (DWC), the presence of fault is detected, but it fails to indicate the location of fault which is overcome in enriched lockstep by triple modular redundancy (TMR). A grid lock technique is proposed for elimination of permanent faults. The efficiency of proposed method is validated using fault injection method and helps in verifying the performance of testable systems. It is based on the correlation between the effects of the SEU fault model with the Stuck-At (SA) faults