Design and analysis of a fifo linked loosely coupled dual processor system

This paper describes the design, implementation and performance analysis of a loosely coupled dual processor system employing FIFO based communication links. Two cards, each supporting a FIFO queue with 8-bit static RAMs and associated counters, are used to connect two IBM PCs. The circuit is controlled entirely by an Altera EP900 which facilitates possible modifications of hardware in the future. Overflow and conflict error conditions trigger and interrupt request and provisions have been made to retry the last operation upon the occurrence of such error conditions. Details on the software developed for interprocessor communication have been provided. The performance of the dual processor system has been analysed with matrix multiplication operations and it is found that when compared to a single processor system, the dual processor system offers a higher throughput when the order of the matrices is seven or above. The system is currently being used as an aid for teaching various concepts on parallel programming and design aspects for developing hardware for multiprocessor systems and subsystems