An Interprocessor Communication Interface for Message Passing via Shared Memory Modules - Design and Performance

In this paper the interprocessor communication interface intended for realization of multiprocessor (MMC) system is described.  The MMC system is implemented as a Fully_Connected_n-side_Pyramid (FCnP). The base of the pyramid consists of n processors and it acts as an accelerator to the host computer that is placed at the top of the pyramid. Communication between any two processors takes place through Shared_Memory_Module (SMM) independently accessed by both processors involved in current data transfer. The SMMs are realized with two-side accessible memory chips of FIFO RAM type. For the processors we use standard Single_Board_Computers (SBC) extended with a communication hardware referred to as the Communication_Module (CM). The main task of the CM is to provide efficient DMA transfer between the SBC's local memory and SMMs. Attaching the CM to the SBC requires only some minor modification of the SBC's hardware. In order to connect one SBC with several SMMs a special bus named Shares_Memory_Bus (SMB) is provided. Higher FCnP's performances, in comparison with the common bus biased MMC systems, are obtained mainly due to: increased communication bandwidth, possibility to use heterogeneous processors, and configuration flexibility of system topology. This paper deals with hardware structure of constituent parts of the communication interface (CM, SMM, and SMB), and system operation concerning the message transfer. Further on, performance evaluation for the proposed communication interface related to system efficiency, communication throughput, and message latency are carried out. Simulation analysis is also included