This thesis presents a methodology to automatically determine a data memory organisation at compiletime, suitable to exploit data reuse and loop-level parallelization, in order to achieve high performanceand low power design for data-dominated applications. Moore?s Law has enabled more and more heterogeneouscomponents integrated on a single chip. However, there are challenges to extract maximumperformance from these hardware resources efficiently. Unlike previous approaches, which mainly focus on making efficient use of computational resources,our focus is on data memory organisation and input-output bandwidth considerations, which are thetypical stumbling block of existing hardware compilation schemes. To optimize accesses to large off-chi...
This thesis investigates parallelism and hardware design trade-offs of parallel and pipelined archit...
Recently, multi-cores chips have become omnipresent in computer systems ranging from high-end server...
In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, ...
This thesis presents a methodology to automatically determine a data memory organisation at compile ...
Abstract—A nonlinear optimization framework is proposed in this paper to automate exploration of the...
The memory system is a major bottleneck in achieving high performance and energy efficiency for vari...
This paper describes our approaches to raise the level of abstraction at which hardwa-re suitable fo...
UnrestrictedConfigurable architectures offer the unique opportunity of realizing hardware designs ta...
The work presented in this thesis focuses on the exploration of alternative architectures and comput...
Abstract. This paper proposes a methodology to study the data reuse quality of task-parallel runtime...
Value locality is the phenomenon that a small number of values occur repeatedly in the same register...
Recent advancements in embedded systems have brought new challenges for industry and academia. In or...
Abstract—This paper proposes a methodology to study the data reuse quality of task-parallel runtimes...
Power has become one of the primary design constraints in modern embedded microprocessors. Many embe...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
This thesis investigates parallelism and hardware design trade-offs of parallel and pipelined archit...
Recently, multi-cores chips have become omnipresent in computer systems ranging from high-end server...
In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, ...
This thesis presents a methodology to automatically determine a data memory organisation at compile ...
Abstract—A nonlinear optimization framework is proposed in this paper to automate exploration of the...
The memory system is a major bottleneck in achieving high performance and energy efficiency for vari...
This paper describes our approaches to raise the level of abstraction at which hardwa-re suitable fo...
UnrestrictedConfigurable architectures offer the unique opportunity of realizing hardware designs ta...
The work presented in this thesis focuses on the exploration of alternative architectures and comput...
Abstract. This paper proposes a methodology to study the data reuse quality of task-parallel runtime...
Value locality is the phenomenon that a small number of values occur repeatedly in the same register...
Recent advancements in embedded systems have brought new challenges for industry and academia. In or...
Abstract—This paper proposes a methodology to study the data reuse quality of task-parallel runtimes...
Power has become one of the primary design constraints in modern embedded microprocessors. Many embe...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
This thesis investigates parallelism and hardware design trade-offs of parallel and pipelined archit...
Recently, multi-cores chips have become omnipresent in computer systems ranging from high-end server...
In this paper, we present a novel linear time algorithm for data remapping that is (i) lightweight, ...