UnrestrictedConfigurable architectures offer the unique opportunity of realizing hardware designs tailored to the specific data and computational patterns of a given application code. These devices have customizable compute fabric, interconnects, and memory subsystems that allow for large amounts of data and computational parallelism. This high degree of concurrency subsequently translates to better performance. The flexibility and configurability of these architectures, however, create a prohibitively large design space when mapping computations expressed in high-level programming languages to these devices. To successfully investigate the best mapping there is a need for high level program analyses and abstractions as well as automated to...
This paper describes an automated approach to hardware design space exploration, through a collabora...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
This thesis presents a methodology to automatically determine a data memory organisation at compilet...
Agency under contract number F30602-98-2-0113 Mapping computations written in high-level programming...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
145 pagesWith the pursuit of improving compute performance under strict power constraints, there is ...
One step in the synthesis for FPGA-based Reconfig-urable Computers (RCs) involves mapping the design...
This paper describes our approaches to raise the level of abstraction at which hardwa-re suitable fo...
In this paper we study the performance improvements and trade-offs derived from an optimized mapping...
Traditional high level synthesis is able to yield high computational resource utilisation and short ...
Abstract—Developing FPGA implementations with an input specification in a high-level programming lan...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
International audienceFinding efficient implementations of data intensive applications, such as rada...
Abstract Finding efficient implementations of data intensive applications, such as radar/sonar signa...
The system efficiency and throughput of most architectures are critically dependent on the ability o...
This paper describes an automated approach to hardware design space exploration, through a collabora...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
This thesis presents a methodology to automatically determine a data memory organisation at compilet...
Agency under contract number F30602-98-2-0113 Mapping computations written in high-level programming...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
145 pagesWith the pursuit of improving compute performance under strict power constraints, there is ...
One step in the synthesis for FPGA-based Reconfig-urable Computers (RCs) involves mapping the design...
This paper describes our approaches to raise the level of abstraction at which hardwa-re suitable fo...
In this paper we study the performance improvements and trade-offs derived from an optimized mapping...
Traditional high level synthesis is able to yield high computational resource utilisation and short ...
Abstract—Developing FPGA implementations with an input specification in a high-level programming lan...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
International audienceFinding efficient implementations of data intensive applications, such as rada...
Abstract Finding efficient implementations of data intensive applications, such as radar/sonar signa...
The system efficiency and throughput of most architectures are critically dependent on the ability o...
This paper describes an automated approach to hardware design space exploration, through a collabora...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
This thesis presents a methodology to automatically determine a data memory organisation at compilet...