Ge pMOSFETs with gate lengths down to 70 nm are fabricated in a Si-like process flow. Reducing the LDD junction depth from 24 to 21 nm effectively reduces short-channel effects. In addition, a reduced source/drain series resistance is obtained using pure boron LDD implants over BF2, resulting in a significant I-ON boost. Benchmarking shows the potential of Ge to outperform (strained) Si, well into the sub-100-nm regime. The 70-nm devices outperform the ITRS requirements for I-ON by 50%, maintaining similar I-OFF, as measured at the source.status: publishe
With the continuous device scaling down as predicted and required by Moore\u27s law, the silicon com...
We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quali...
We report the first demonstration of GeSn pMOSFETs. Key highlights of this work also includes a180°C...
[[abstract]]The reduction of transient enhanced diffusion (TED) and suppression of short-channel eff...
The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconduct...
We report high performance Ge p(+)/n junctions using a single, cryogenic (-100 degrees C) boron ion ...
In this work we explore the potential of the emerging Germanium technology for logic circuits. We in...
SiGe and Ge source/drain (S/D) stressors have been used to boost the Si channel pMOSFET drive curren...
To reach future low power operation at &le0.5 V, high mobility InGaAs nMOS and Ge pMOS were prop...
As device dimensions are scaled beyond the 45nm node, new device architectures and new materials ne...
The electrical characteristics of germanium (Ge) pMOSFETs with high-kappa dielectric and gate length...
Power dissipation has become one of the most significant impediments to continued scaling of complem...
As the CMOS transistor scaling is approaching its physical limits, the semiconductor industry is for...
Compressively strained Ge long channel ring-type pMOSFETs with high-κ Si/SiO2/HfO2/TiN gate stacks a...
Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investiga...
With the continuous device scaling down as predicted and required by Moore\u27s law, the silicon com...
We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quali...
We report the first demonstration of GeSn pMOSFETs. Key highlights of this work also includes a180°C...
[[abstract]]The reduction of transient enhanced diffusion (TED) and suppression of short-channel eff...
The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconduct...
We report high performance Ge p(+)/n junctions using a single, cryogenic (-100 degrees C) boron ion ...
In this work we explore the potential of the emerging Germanium technology for logic circuits. We in...
SiGe and Ge source/drain (S/D) stressors have been used to boost the Si channel pMOSFET drive curren...
To reach future low power operation at &le0.5 V, high mobility InGaAs nMOS and Ge pMOS were prop...
As device dimensions are scaled beyond the 45nm node, new device architectures and new materials ne...
The electrical characteristics of germanium (Ge) pMOSFETs with high-kappa dielectric and gate length...
Power dissipation has become one of the most significant impediments to continued scaling of complem...
As the CMOS transistor scaling is approaching its physical limits, the semiconductor industry is for...
Compressively strained Ge long channel ring-type pMOSFETs with high-κ Si/SiO2/HfO2/TiN gate stacks a...
Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investiga...
With the continuous device scaling down as predicted and required by Moore\u27s law, the silicon com...
We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quali...
We report the first demonstration of GeSn pMOSFETs. Key highlights of this work also includes a180°C...