Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resources, pipelining optimization without (or with minimal) resource sharing can give significant advantages in performance. High-level synthesis of CAL-programs is particularly popular in computation intensive applications (e.g., image and video processing, cryptography, wireless communication, etc.) where feedback actors with data flows at input and output ports represent loop-like behavior. In this work, we propose techniques for transforming, analysis, speculatively pipelining and optimizin...
Based on the model of synchronous data flow (SDF) [13], so called single appearance schedules are kn...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable ...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
An analysis of computational pipelines and their optimization methods has been performed. A class of...
High-level synthesis is a powerful tool for increasing productivity in digital hardware design. Howe...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
Loop pipelining is widely adopted as a key optimization method in high-level synthesis (HLS). Howeve...
Instruction scheduling and Software pipelining are important compilation techniques which reorder in...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
The scheduling of loops for architectures which support instruction level parallelism is an importan...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
Although there are widely known solutions for dataflow-dominated resource constrained high-level syn...
Based on the model of synchronous data flow (SDF) [13], so called single appearance schedules are kn...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable ...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
An analysis of computational pipelines and their optimization methods has been performed. A class of...
High-level synthesis is a powerful tool for increasing productivity in digital hardware design. Howe...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
Loop pipelining is widely adopted as a key optimization method in high-level synthesis (HLS). Howeve...
Instruction scheduling and Software pipelining are important compilation techniques which reorder in...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
The scheduling of loops for architectures which support instruction level parallelism is an importan...
This paper addresses the problem of trading-off between the minimization of program and data memory ...
Although there are widely known solutions for dataflow-dominated resource constrained high-level syn...
Based on the model of synchronous data flow (SDF) [13], so called single appearance schedules are kn...
High-level synthesis is a novel method to generate a RT-level hardware description automatically fro...
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable ...