Although there are widely known solutions for dataflow-dominated resource constrained high-level synthesis (HLS) problems, optimization of hardware resources under time-constraints in controlintensive systems is still a challenge. This paper examines the case when functional pipelining is used to increase the throughput of the system. The traditional concept of mutually exclusive conditional branches must be dropped and new methods are needed to exploit the resource sharing possibilities of conditional branches. We developed new methodologies able to exploit the resource sharing possibilities under these circumstances and extended the two schedulers and the allocation module of the HLS tool PIPE to handle arbitrarily nested conditional stru...
High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses s...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
[[abstract]]An algorithm for pipelining loop execution in the presence of loop carried dependences i...
Although there are widely known solutions for dataflow-dominated resource constrained high-level syn...
In high-level synthesis (HLS), loop pipelining allows multiple iterations of a loop to be executed c...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
Many high level synthesis systems produce designs without any consideration for the underlying archi...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
We address the prblem of time-stationary control synthesis for pipelined data paths. Control synthes...
This paper presents a model and a method for the allocation during the high level datapath synthesis...
This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput,...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
Recent research results have seen the application of parallelizing techniques to high-level synthesi...
[[abstract]]Pipelining is an effective method to optimize the execution of a loop, especially for di...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses s...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
[[abstract]]An algorithm for pipelining loop execution in the presence of loop carried dependences i...
Although there are widely known solutions for dataflow-dominated resource constrained high-level syn...
In high-level synthesis (HLS), loop pipelining allows multiple iterations of a loop to be executed c...
International audienceAs hardware designs get increasingly complex and time-to-market constraints ge...
Many high level synthesis systems produce designs without any consideration for the underlying archi...
High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. Th...
We address the prblem of time-stationary control synthesis for pipelined data paths. Control synthes...
This paper presents a model and a method for the allocation during the high level datapath synthesis...
This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput,...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
Recent research results have seen the application of parallelizing techniques to high-level synthesi...
[[abstract]]Pipelining is an effective method to optimize the execution of a loop, especially for di...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
High-level synthesis becomes increasingly important in the area of VLSI CAD. This thesis addresses s...
This paper introduces a new methodology for pipeline synthesis with applications to data flow high-l...
[[abstract]]An algorithm for pipelining loop execution in the presence of loop carried dependences i...