Fault injection studies and vulnerability analyses have been used to estimate the reliability of data structures in memory. We survey these metrics and look at their adequacy to describe the data stored in ECC-protected memory. We also introduce FEA, a new metric improving on the memory derating factor by ignoring a class of false errors. We measure all metrics using simulations and compare them to the outcomes of injecting errors in real runs. This in-depth study reveals that FEA provides more accurate results than any state-of-the-art vulnerability metric. Furthermore, FEA gives an upper bound on the failure probability due to an error in memory, making this metric a tool of choice to quantify memory vulnerability. Finally, we show that i...
In the field of cryptography engineering, implementation-based attacks are a major concern due to th...
Error Correcting Code (ECC) techniques aims at providing concurrent correction and detection of sing...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
To face future reliability challenges, it is necessary to quantify the risk of error in any part of ...
In most safety-critical systems, the robustness and the confidentiality of the application code are ...
<p>Computing systems use dynamic random-access memory (DRAM) as main memory. As prior works have sho...
Memory leaks and memory corruption are two major forms of software bugs that severely threaten syste...
International audienceError-correcting codes (ECC) offer an efficient way to improve the reliability...
Memory hardware reliability is an indispensable part of whole-system dependability. This paper prese...
International audienceWith the progress of the technology, the presence of transient faults (e.g. bi...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2012In moder...
In this book we examine a number of vulnerabilities in C-like languages that can be exploited by att...
ISBN 978-1-4673-5542-1International audienceIn modern SoCs embedded memories should be repaired to a...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...
Abstract–Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundanc...
In the field of cryptography engineering, implementation-based attacks are a major concern due to th...
Error Correcting Code (ECC) techniques aims at providing concurrent correction and detection of sing...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...
To face future reliability challenges, it is necessary to quantify the risk of error in any part of ...
In most safety-critical systems, the robustness and the confidentiality of the application code are ...
<p>Computing systems use dynamic random-access memory (DRAM) as main memory. As prior works have sho...
Memory leaks and memory corruption are two major forms of software bugs that severely threaten syste...
International audienceError-correcting codes (ECC) offer an efficient way to improve the reliability...
Memory hardware reliability is an indispensable part of whole-system dependability. This paper prese...
International audienceWith the progress of the technology, the presence of transient faults (e.g. bi...
Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2012In moder...
In this book we examine a number of vulnerabilities in C-like languages that can be exploited by att...
ISBN 978-1-4673-5542-1International audienceIn modern SoCs embedded memories should be repaired to a...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...
Abstract–Post-silicon healing techniques that rely on built-in redundancy (e.g. row/column redundanc...
In the field of cryptography engineering, implementation-based attacks are a major concern due to th...
Error Correcting Code (ECC) techniques aims at providing concurrent correction and detection of sing...
2012-01-31Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is...