Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardware mechanisms to alleviate the impact of long memory latencies, but despite decades of research, significant headroom remains. In this thesis, we show how we can significantly improve caching and prefetching by exploiting a long history of the program's behavior. Towards this end, we define new learning goals that fully exploit long-term information, and we propose history representations that make it feasible to track and manipulate long histories. Based on these insights, we advance the state-of-the-art for three important memory system optimizations. For cache replacement, where existing solutions have relied on simplistic heuristics, o...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
Data Prefetchers identify and make use of any regularity present in the history/training stream to p...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardwa...
Memory accesses continue to be a performance bottleneck for many programs, and prefetching is an ef...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
The “Memory Wall”, the vast gulf between processor execution speed and memory latency, has led to th...
Techniques for analyzing and improving memory referencing behavior continue to be important for achi...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...
The memory system remains a bottleneck in modern computer systems. Traditionally, designers have use...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
textModern computer systems spend a substantial fraction of their running time waiting for data from...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
Data prefetching is an effective way to bridge the increasing performance gap between processor and ...
grantor: University of TorontoThe latency of accessing instructions and data from the memo...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
Data Prefetchers identify and make use of any regularity present in the history/training stream to p...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardwa...
Memory accesses continue to be a performance bottleneck for many programs, and prefetching is an ef...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
The “Memory Wall”, the vast gulf between processor execution speed and memory latency, has led to th...
Techniques for analyzing and improving memory referencing behavior continue to be important for achi...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...
The memory system remains a bottleneck in modern computer systems. Traditionally, designers have use...
CPU speeds double approximately every eighteen months, while main memory speeds double only about ev...
textModern computer systems spend a substantial fraction of their running time waiting for data from...
With off-chip memory access taking 100's of processor cycles, getting data to the processor in a tim...
Data prefetching is an effective way to bridge the increasing performance gap between processor and ...
grantor: University of TorontoThe latency of accessing instructions and data from the memo...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
Data Prefetchers identify and make use of any regularity present in the history/training stream to p...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...