Selective prefetching: prefetching when only required

The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xplore database licensed by University Libraries: http://libcat.wichita.edu/vwebv/holdingsInfo?bibId=1045954Cache memories are commonly used to reduce the number of slower lower-level memory accesses, thereby improving the memory hierarchy performance. However, high cache miss-ratio can severely degrade system performance. It is therefore necessary to anticipate the cache misses to reduce their frequency. Prefetching, is one such technique, which allows memory systems to import data into the cache before the processor needs it. Aggressive prefetching can significantly reduce cache misses but may lead to cache pollution and also increase memory traffic. An innovative hardware-based prefetching technique is proposed which overcomes these problems while providing improved cache hit-rate. Our trace driven simulations show an improvement of around 60% in the miss rates for an instruction cache employing the LRU-FP block replacement algorithm with the proposed pre-fetch scheme as compared to the miss rates obtained due to a sequential prefetch mechanismPeer reviewed articl