Hybrid Prefetcher

In the last century great progress was achieved in developing processors with extremely high computational capabilities. However, one of the biggest suppressors of those capabilities is the memory subsystem. Many approaches are used to bypass this constraint. Some took the approach of parallelism, while others use cache optimizations to minimize memory latency. An additional approach, and the one I will elaborate in this paper, is prefetching. In this paper I will only talk about hardware prefetching, which relies on additional hardware to preform prefetching and is preformed during runtime. In my prefetcher design I try to deliver the best memory access pattern recognition, while minimizing the impact on memory bandwidth and cache pollution. To achieve this I created a hybrid between a correlated prefetcher and a stride prefetcher. Since both approaches have their advantages and disadvantages, I tried to achieve a design that will help mask the disadvantages and expose the advantages of both approaches. Also, I utilized a more calculated approach rather than brute force to perfom the necessary prefetches.unpublishednot peer reviewedU of I OnlyUndergraduate senior thesis not recommended for open acces