Data prefetching is an effective way to bridge the increasing performance gap between processor and memory. As computing power is increasing much faster than memory performance, we suggest that it is time to have a dedicated cache to store data access histories and to serve prefetching to mask data access latency effectively. We thus propose a new cache structure, named Data Access History Cache (DAHC), and study its associated prefetching mechanisms. The DAHC behaves as a cache for recent reference information instead of as a traditional cache for instructions or data. Theoretically, it is capable of supporting many well known history-based prefetching algorithms, especially adaptive and aggressive approaches. We have carried out simulatio...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Memory accesses continue to be a performance bottleneck for many programs, and prefetching is an ef...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
Data prefetching has been considered an effective way to mask data access latency caused by cache mi...
Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardwa...
Data-intensive applications often exhibit memory referencing patterns with little data reuse, result...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
Prefetching disk blocks to main memory will become increasingly important to overcome the widening g...
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems...
Data prefetching has been considered an effective way to cross the performance gap between processor...
Conventional cache prefetching approaches can be either hardware-based, generally by using a one-blo...
The performance of superscalar processors is more sensitive to the memory system delay than their si...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Memory accesses continue to be a performance bottleneck for many programs, and prefetching is an ef...
The large number of cache misses of current applications coupled with the increasing cache miss late...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
Data prefetching has been considered an effective way to mask data access latency caused by cache mi...
Memory latency is a key bottleneck for many programs. Caching and prefetching are two popular hardwa...
Data-intensive applications often exhibit memory referencing patterns with little data reuse, result...
A well known performance bottleneck in computer architecture is the so-called memory wall. This term...
In this paper, we present our design of a high performance prefetcher, which exploits various locali...
In this dissertation, we provide hardware solutions to increase the efficiency of the cache hierarch...
Prefetching disk blocks to main memory will become increasingly important to overcome the widening g...
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems...
Data prefetching has been considered an effective way to cross the performance gap between processor...
Conventional cache prefetching approaches can be either hardware-based, generally by using a one-blo...
The performance of superscalar processors is more sensitive to the memory system delay than their si...
The gap between processor and memory speed appears as a serious bottleneck in improving the performa...
Memory accesses continue to be a performance bottleneck for many programs, and prefetching is an ef...
The large number of cache misses of current applications coupled with the increasing cache miss late...