An effective on-chip preloading scheme to reduce data access penalty

Conventional cache prefetching approaches can be either hardware-based, generally by using a one-block-Iookahead technique, or compiler-directed, with inser-tions of non-blocking prefetch instructions. We intro-duce a new hardware scheme based on the prediction of the execution of the instruction stream and associated operand references. It consists of a reference predic-tion table and a look-ahead program counter and its associated logic. With this scheme, data with regu-lar access patterns is preloaded, independently of the stride size, and preloading of data with irregular access patterns is prevented. We evaluate our design through trace driven simulation by comparing it with a pure data cache approach under three different memory ac-cess models. Our experiments show that this scheme is very effective for reducing the data access penalty for scientific programs and that is has moderate success for other applications.