In this paper we describe a method to combine dictionary coding and partial LFSR reseeding to improve the compression efficiency for test data compression. We also present a fast matrix calculation method which significantly reduces the computation time to find a solution for partial LFSR reseeding. Experimental results on ISCAS89 benchmark circuits show that our approach is better than either dictionary coding or LFSR reseeding, and outperforms several test data compression methods proposed recently
... reseeding architecture is the limited seed efficiency due to the variance in the number of speci...
[[abstract]]This paper presents a low power strategy for test data compression and a new decompressi...
Test data compression is an effective methodology for reducing test data volume and testing time. Th...
Abstract—This paper presents a new low-power test-data-compression scheme based on linear feedback s...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test da...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test da...
Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. Howe...
An approach for input data compaction in the testing of circuits using scan and partial scan has rec...
textThis dissertation considers the problem of reducing the storage as well as the bandwidth (data ...
We present a new test data compression and decompression architecture based on a novel and efficient...
In testing there are two primary domains one is reducing input test data volume and next is reducing...
textAs the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and ...
textThis paper investigates the cost-tradeoffs of implementing a test data compression technique pr...
textThis paper investigates the cost-tradeoffs of implementing a test data compression technique pr...
textAs the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and ...
... reseeding architecture is the limited seed efficiency due to the variance in the number of speci...
[[abstract]]This paper presents a low power strategy for test data compression and a new decompressi...
Test data compression is an effective methodology for reducing test data volume and testing time. Th...
Abstract—This paper presents a new low-power test-data-compression scheme based on linear feedback s...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test da...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test da...
Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. Howe...
An approach for input data compaction in the testing of circuits using scan and partial scan has rec...
textThis dissertation considers the problem of reducing the storage as well as the bandwidth (data ...
We present a new test data compression and decompression architecture based on a novel and efficient...
In testing there are two primary domains one is reducing input test data volume and next is reducing...
textAs the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and ...
textThis paper investigates the cost-tradeoffs of implementing a test data compression technique pr...
textThis paper investigates the cost-tradeoffs of implementing a test data compression technique pr...
textAs the size and complexity of systems-on-a-chips (SOCs) continue to grow, test data volume and ...
... reseeding architecture is the limited seed efficiency due to the variance in the number of speci...
[[abstract]]This paper presents a low power strategy for test data compression and a new decompressi...
Test data compression is an effective methodology for reducing test data volume and testing time. Th...