Test data compression is an effective methodology for reducing test data volume and testing time. The author presents a new test data compression technique based on block merging. The technique capitalises on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0s or all 1s. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test-dataindependent. Experimental results on benchmark circuits demonstrate the effectiveness of the...
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-b...
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test ...
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data ...
In this paper, we present a new test data compression technique based on block merging. The techniqu...
In this paper, we present a new test data compression technique based on block merging. The techniqu...
In this paper, we present a new test data compression technique based on block merging. The techniqu...
AbstractTest data compression is a major scenario in all system-on-a-chip (SOC) designs for reducing...
It has been seen that the test data compression has been an emerging need of VLSI field and hence th...
In this paper, we present a novel compression method and a low-cost decompression architecture that ...
textSequential linear decompressors are widely used to implement test compression. Bits stored on th...
textSequential linear decompressors are widely used to implement test compression. Bits stored on th...
This paper presents a new test data compression technique based on a compressioncode that uses exact...
AbstractTest data compression is a major scenario in all system-on-a-chip (SOC) designs for reducing...
textThis dissertation considers the problem of reducing the storage as well as the bandwidth (data ...
This paper presents a test input data compression technique, which can be used to reduce input test ...
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-b...
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test ...
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data ...
In this paper, we present a new test data compression technique based on block merging. The techniqu...
In this paper, we present a new test data compression technique based on block merging. The techniqu...
In this paper, we present a new test data compression technique based on block merging. The techniqu...
AbstractTest data compression is a major scenario in all system-on-a-chip (SOC) designs for reducing...
It has been seen that the test data compression has been an emerging need of VLSI field and hence th...
In this paper, we present a novel compression method and a low-cost decompression architecture that ...
textSequential linear decompressors are widely used to implement test compression. Bits stored on th...
textSequential linear decompressors are widely used to implement test compression. Bits stored on th...
This paper presents a new test data compression technique based on a compressioncode that uses exact...
AbstractTest data compression is a major scenario in all system-on-a-chip (SOC) designs for reducing...
textThis dissertation considers the problem of reducing the storage as well as the bandwidth (data ...
This paper presents a test input data compression technique, which can be used to reduce input test ...
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-b...
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test ...
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data ...