Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is first divided into regular partitions. Then two parts of the schedule, the ALU part and the memory part, are produced and balanced to produce an overall schedule with high throughput. These two parts are executed simultaneously, and hence the remote memory latency are overlapped. We study the optimal partition shape and size so that a well balanced overall schedule can be obtained. Experiments on DSP benchmarks show that the proposed methodology consistently produces optimal or near optimal solutions.
This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput,...
We study integrated prefetching and caching problems following the work of Cao et. al. [3] and Kimbr...
Although shared memory programming models show good programmability compared to message passing prog...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
In this paper, we propose a novel loop scheduling technique based on multi-dimensional retiming in a...
The widening gap between processor and memory performance is the main bottleneck for modern computer...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
The paper proposes a scheme to tolerate the slow memory access latency for loop intensive applicatio...
As the gap between processor and memory speeds widens, program performance is increasingly dependent...
Predictable execution models have been proposed over the years to achieve contention-free execution ...
During the past decades of research in Real-Time systems, non-preemptive scheduling and fully preemp...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...
In computer systems, latency tolerance is the use of concurrency to achieve high performance in spit...
grantor: University of TorontoA key obstacle to achieving high performance on software dis...
Software pipelining is a loop scheduling technique that extracts parallelism from loops by overlappi...
This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput,...
We study integrated prefetching and caching problems following the work of Cao et. al. [3] and Kimbr...
Although shared memory programming models show good programmability compared to message passing prog...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
In this paper, we propose a novel loop scheduling technique based on multi-dimensional retiming in a...
The widening gap between processor and memory performance is the main bottleneck for modern computer...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
The paper proposes a scheme to tolerate the slow memory access latency for loop intensive applicatio...
As the gap between processor and memory speeds widens, program performance is increasingly dependent...
Predictable execution models have been proposed over the years to achieve contention-free execution ...
During the past decades of research in Real-Time systems, non-preemptive scheduling and fully preemp...
Achieving optimal throughput by extracting parallelism in behavioral synthesis often exaggerates mem...
In computer systems, latency tolerance is the use of concurrency to achieve high performance in spit...
grantor: University of TorontoA key obstacle to achieving high performance on software dis...
Software pipelining is a loop scheduling technique that extracts parallelism from loops by overlappi...
This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput,...
We study integrated prefetching and caching problems following the work of Cao et. al. [3] and Kimbr...
Although shared memory programming models show good programmability compared to message passing prog...