In this paper, we propose a novel loop scheduling technique based on multi-dimensional retiming in a balanced fashion, which considers the computation schedule and memory access schedule simultaneously. Experiments show that the proposed technique which combines the data prefetching and retiming is successful in hiding memory latency and improving the overall performance. Comparing with the traditional list scheduling algorithm, the average improvement is 28%. 1 Introduction In the past few years, the processing time of a processor has increased more rapidly than the speed to access the memory. In a system with a local and remote memory, the program execution time become significantly depending on the remote-memory access latency. Data pre...
Memory-bound applications heavily depend on the bandwidth of the system in order to achieve high per...
Pointer-chasing applications tend to traverse composed data structures consisting of multiple indepe...
International Conference on Embedded and Ubiquitous Computing, EUC 2005, Nagasaki, 6-9 December 2005...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
The widening gap between processor and memory performance is the main bottleneck for modern computer...
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the ...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
International audience— Multidimensional retiming is an efficient optimization approach that ensures...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
Link to published version: http://ieeexplore.ieee.org/iel2/390/6075/00236705.pdf?tp=&arnumber=236705...
This paper presents a novel pointer prefetching technique, called multi-chain prefetching. Multi-cha...
As the gap between processor and memory speeds widens, program performance is increasingly dependent...
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems...
The gap between CPU speed and memory speed in modern computer systems is widening as new generations...
Predictable execution models have been proposed over the years to achieve contention-free execution ...
Memory-bound applications heavily depend on the bandwidth of the system in order to achieve high per...
Pointer-chasing applications tend to traverse composed data structures consisting of multiple indepe...
International Conference on Embedded and Ubiquitous Computing, EUC 2005, Nagasaki, 6-9 December 2005...
The large latency of memory accesses in modern computers is a key obstacle in achieving high process...
The widening gap between processor and memory performance is the main bottleneck for modern computer...
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the ...
Over the last 20 years, the performance gap between CPU and memory has been steadily increasing. As ...
International audience— Multidimensional retiming is an efficient optimization approach that ensures...
Recent technological advances are such that the gap between processor cycle times and memory cycle t...
Link to published version: http://ieeexplore.ieee.org/iel2/390/6075/00236705.pdf?tp=&arnumber=236705...
This paper presents a novel pointer prefetching technique, called multi-chain prefetching. Multi-cha...
As the gap between processor and memory speeds widens, program performance is increasingly dependent...
Memory latency has always been a major issue in shared-memory multiprocessors and high-speed systems...
The gap between CPU speed and memory speed in modern computer systems is widening as new generations...
Predictable execution models have been proposed over the years to achieve contention-free execution ...
Memory-bound applications heavily depend on the bandwidth of the system in order to achieve high per...
Pointer-chasing applications tend to traverse composed data structures consisting of multiple indepe...
International Conference on Embedded and Ubiquitous Computing, EUC 2005, Nagasaki, 6-9 December 2005...