We revisit the idea of using small line buffers in-front of caches. We propose ReCast, a tiny tag set cache that filters a significant number of tag probes to the L2 tag array thus reducing power. The key contribution in ReCast is S-Shift, a simple indexing function (no logic involved just wires) that greatly improves the utility of line buffers with no additional hardware cost. S-Shift can be viewed as a technique for emulating larger cache blocks and hence exploiting more spatial locality but without paying the penalties of actually using a larger L2 cache block. Using several SPEC CPU2000 applications and a model of an aggressive, dynamicallyscheduled, superscalar processor we demonstrate that a practical ReCast organization can signific...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. I...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
In current processors, the cache controller, which contains the cache directory and other logic such...
Most newly announced microprocessors manipulate 64-bit virtual addresses and the width of physical a...
A new dynamic cache resizing scheme for low-power CAM-tag caches is introduced. A control algorithm ...
Energy efficiency is a first-order design goal for nearly all classes of processors, but it is parti...
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache s...
The need for energy efficiency continues to grow for many classes of processors, including those for...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-mi...
On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power....
Most newly announced high erformance micro ro-/ {cessors sup ort 64-bit virtual ad resses and the wi...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. I...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
In current processors, the cache controller, which contains the cache directory and other logic such...
Most newly announced microprocessors manipulate 64-bit virtual addresses and the width of physical a...
A new dynamic cache resizing scheme for low-power CAM-tag caches is introduced. A control algorithm ...
Energy efficiency is a first-order design goal for nearly all classes of processors, but it is parti...
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache s...
The need for energy efficiency continues to grow for many classes of processors, including those for...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-mi...
On chip caches in modern processors account for a sizable fraction of the dynamic and leakage power....
Most newly announced high erformance micro ro-/ {cessors sup ort 64-bit virtual ad resses and the wi...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Sectored caches have been used for many years in order to reduce the tag volume needed in a cache. I...