In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resizing is accompanied by a non-uniform remapping of memory into the resized cache, thus avoiding misses to sets/lines that are shut off. The paper first provides an analysis into the causes of energy inefficiencies revealing a simple model for improving efficiency. Based on this model we propose the concept of “folding ”- memory regions mapping to disjoint cache resources are combined to share cache sets producing a new placement function. Folding enables powering down cache sets at the expense of possibly increasing conflict misses. Effective folding heuristics can s...
In this paper we propose a technique that uses an ad-ditional mini cache located between the I-Cache...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve ...
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache ...
With the fast increase of the transistors these years, the power consumption of the IC chip also inc...
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent res...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
In this paper, we provide a novel compile-time data remapping algorithm that runs in linear time. ...
Managing the energy-performance tradeoff has become a major challenge on embedded systems. The cache...
Cache memory is one of the most important components of a computer system. The cache allows quickly...
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from ...
Buffer cache replacement schemes play an important role in conserving memory energy. Conventional al...
Memory subsystem with larger capacity and deeper hierarchy has been designed to achieve the maximum ...
In today’s computer, there are larger sizes of the cache are using on the chip. Moreover, there is s...
In this paper we propose a technique that uses an ad-ditional mini cache located between the I-Cache...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve ...
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache ...
With the fast increase of the transistors these years, the power consumption of the IC chip also inc...
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent res...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
In this paper, we provide a novel compile-time data remapping algorithm that runs in linear time. ...
Managing the energy-performance tradeoff has become a major challenge on embedded systems. The cache...
Cache memory is one of the most important components of a computer system. The cache allows quickly...
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from ...
Buffer cache replacement schemes play an important role in conserving memory energy. Conventional al...
Memory subsystem with larger capacity and deeper hierarchy has been designed to achieve the maximum ...
In today’s computer, there are larger sizes of the cache are using on the chip. Moreover, there is s...
In this paper we propose a technique that uses an ad-ditional mini cache located between the I-Cache...
Minimizing power consumption continues to grow as a critical design issue for many platforms, from e...
Hardware designers are constantly looking for ways to squeeze waste out of architectures to achieve ...