Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. This paper proposes exclusive cache model that reduces the energy consumption over the tag cache model. The proposed model assumes two level exclusive cache with tag cache in level one. The tag cache consists of tag information of all cache levels. It is stored in cache in level one. An address is checked in tag cache and the corresponding line is accessed. On miss, the line is placed as in exclusive cache case updating the tag cache. The proposed model compares subsets of tag during address mapping. This turns on selectively the comparison circuitry in tag cache selectively saving energy consumption. A mathematical model is developed for the ...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
MasterWe present novel ways to predict both cache hits and misses during tag comparison in a high-as...
The need for energy efficiency continues to grow for many classes of processors, including those for...
For the two level two type data cache model proposed in literature, the two cache levels are accesse...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
On-chip caches have been playing an important role in achieving high performance processors. In part...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
This paper presents a novel structure for partial tag comparison cache. By triggering partial compar...
The number of battery powered devices is growing significantly and these devices require energy-effi...
ABSTRACT This paper proposes a history-based tag-comparison scheme for reducing energy consumption o...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-...
A new dynamic cache resizing scheme for low-power CAM-tag caches is introduced. A control algorithm ...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
MasterWe present novel ways to predict both cache hits and misses during tag comparison in a high-as...
The need for energy efficiency continues to grow for many classes of processors, including those for...
For the two level two type data cache model proposed in literature, the two cache levels are accesse...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
[EN] Power consumption in current high-performance chip multiprocessors (CMPs) has become a major de...
On-chip caches have been playing an important role in achieving high performance processors. In part...
SUMMARY Energy consumption has become an important design consideration in modern processors. Theref...
This paper presents a novel structure for partial tag comparison cache. By triggering partial compar...
The number of battery powered devices is growing significantly and these devices require energy-effi...
ABSTRACT This paper proposes a history-based tag-comparison scheme for reducing energy consumption o...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
This paper proposes a history-based tag-comparison scheme for reducing energy consumption of direct-...
A new dynamic cache resizing scheme for low-power CAM-tag caches is introduced. A control algorithm ...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
MasterWe present novel ways to predict both cache hits and misses during tag comparison in a high-as...
The need for energy efficiency continues to grow for many classes of processors, including those for...