A new dynamic cache resizing scheme for low-power CAM-tag caches is introduced. A control algorithm that is only activated on cache misses uses a duplicate set of tags, the miss tags, to minimize active cache size while sustaining close to the same hit rate as a full size cache. The cache partitioning mechanism saves both switching and leakage energy in unused partitions with little impact on cycle time. Simulation results show that the scheme saves 28{56 % of data cache energy and 34{49 % of instruction cache energy with minimal performance impact. Categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles|Associativ
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
There is an on-going debate about which consumes less en-ergy: a RAM-tagged associative cache with a...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Content Addressable Memories (CAM) are widely used for the tag portions in highly associative caches...
In current processors, the cache controller, which contains the cache directory and other logic such...
Caches contribute to much of a microprocessor system's power and energy consumption. We have de...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
Abstract—A novel, low-energy content addressable memory (CAM) structure is presented which achieves ...
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache s...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
In this paper we present a software-directed customization method-ology for minimizing the energy di...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...
There is an on-going debate about which consumes less en-ergy: a RAM-tagged associative cache with a...
Abstract: Caches contribute to much of a microprocessor system's set-associative cache. However...
Content Addressable Memories (CAM) are widely used for the tag portions in highly associative caches...
In current processors, the cache controller, which contains the cache directory and other logic such...
Caches contribute to much of a microprocessor system's power and energy consumption. We have de...
We propose a novel energy-efficient memory architecture which relies on the use of cache with a redu...
Abstract—A novel, low-energy content addressable memory (CAM) structure is presented which achieves ...
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache s...
Energy consumption in caches is widely studied topic. The access to a cache line consumes energy. Th...
[[abstract]]Conventional set‐associative caches, with higher associativity, provide lower miss rates...
In this paper we present a software-directed customization method-ology for minimizing the energy di...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper presents a technique for minimizing chip-area cost of implementing an on-chip cache memor...
This paper proposes an architecture for low-power direct-mapped instruction caches, called “history-...
textOne of the major limiters to computer systems and systems on chip (SOC) designs is accessing the...