Fault Aware Instruction Placement for Static Architectures

Aggressive technology scaling, rising clock frequencies, and the continued increase in microprocessor power density threaten both manufacturing yield rates and long-term reliability of integrated circuits. While defects in dynamically scheduled microprocessor architectures can be tolerated using mechanisms that are transparent to software, static architectures create different opportunities and challenges for reliability management. This paper proposes to expose the defective hardware configuration in a static architecture to the compiler, which can perform efficient fault reconfiguration through intelligent instruction scheduling. We conducted our studies on the TRIPS architecture whose computation core consists of a two-dimensional array of ALUs. The compiler generates blocks of instructions that are statically placed on the distributed ALU array, which are then executed dynamically in dataflow order. We consider two fault models, one in which only the computation elements can fail, and another that also allows faults in the communication channels. We examine scheduling algorithms that can avoid the faulty resources by exploiting the spatial redundancy inherent in the computation substrate. For a set of microbenchmarks, preliminary results demonstrate that our algorithms can reschedule the assembly code to tolerate execution unit faults with negligible loss in performance.