Scheduling reusable instructions for power reduction

In this paper, we propose a new issue queue design that is capable of scheduling reusable instructions. Once the is-sue queue is reusing instructions, no instruction cache ac-cess is needed since the instructions are supplied by the is-sue queue itself. Furthermore, dynamic branch prediction and instruction decoding can also be avoided permitting the gating of the front-end stages of the pipeline (the stages be-fore register renaming). Results using array-intensive codes show that up to 82 % of the total execution cycles, the pipeline front-end can be gated, providing a power reduc-tion of 72 % in the instruction cache, 33 % in the branch pre-dictor, and 21 % in the issue queue, respectively, at a small performance cost. Our analysis of compiler optimizations indicates that the power savings can be further improved by using optimized code. 1