Energy-Efficient Instruction Scheduling Utilizing Cache Miss Information

Current microprocessors require both high performance and low-power consumption. In order to reduce energy consump-tion with maintaining computing performance, we propose to utilize the information regarding instruction criticality. Microprocessors we are proposing have two types of func-tional units distinguished in terms of their execution latency and power consumption. Only critical instructions are exe-cuted on power-hungry functional units, and thus the total energy consumption can be reduced without severe perfor-mance loss. In order to achieve large energy reduction, it is required to execute instructions on power-efficient units as frequently as possible. In this paper, we propose a new instruction scheduling method utilizing cache miss informa-tion over the above mentioned scheduling technique. As a performance gap between microprocessors and main mem-ories is increasing, it is possible that critical instructions are executed in power-efficient units as well as non-critical ones while main memory access is occurring. Our simu-lation results reveal that the modified instruction schedul-ing achieves 27.3 % ED2P reduction with 1.4 % performance degradation