Prédiction de l'adresse des lectures pour tolérer la latence des accès mémoire Prediction of addresses for speculating loads

One major restriction to the performance of out-of-order superscalar processors is the latency of loads. We propose to tolerate these latencies by executing loads earlier using a mechanism we called address prediction. The prediction of the address of the data to be loaded is made during the dispatch using the address of the instruction. Thus, loads are executed earlier and, provided the prediction is good, their result might be used as soon as the address is verified. The address prediction technique looks like prefetching techniques but presents a higher gain because the value is directly fetched into the processor rather than in the L1 cache only. Keywords: Architecture, out-of-order superscalar processors, data preloading Table des mati`eres I Pr'ediction de l'adresse des lectures pour tol'erer la latence des acc`es m'emoire 1 1 Introduction 3 1.1 Etat de l'art : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 1.2 Notre solution : : : : : : : : : : : : : : : : : : : ..