Add to ORKGMitigating the effect of the large latency of load instructions is one of challenges of micro-processor designers. This thesis analyses one of the alternatives for tackling this problem: address prediction and speculative execution. Several authors have noticed that the effective addresses computed by the load instructions are quite predictable. First of all, we study why this predictability appears; our study tries to detect the high-level language structures that are compiled into predictable load instructions. We also analyse the conventional address predictors in order to determine which address predictors are most appropriate for the typical applications. Our study continues by proposing address predictors that use their storage struct...
The execution time of programs that have large working sets is substantially increased by the overhe...
Efficient data supply to the processor is the one of the keys to achieve high performance. However, ...
Processor performance is directly impacted by the latency of the memory system. As processor core cy...
. Data speculation refers to the execution of an instruction before some logically preceding instruc...
One major restriction to the performance of out-of-order superscalar processors is the latency of lo...
Two orthogonal hardware techniques, table-based address prediction and early address calculation, fo...
Uno de los mayores retos que debe ser afrontado por los diseñadores de micro-procesadores es el de m...
Abstract — Recent works have proposed the use of prediction techniques to execute speculatively true...
Modern processors rely heavily on speculation to provide performance. Techniques such as branch pred...
While runahead execution is effective at parallelizing independent long-latency cache misses, it is ...
Branch prediction feeds a speculative execution processor core with instructions. Branch mispredicti...
In this correspondence, we propose design techniques that may significantly simplify the cache acces...
For many programs, especially integer codes, untolerated load instruction latencies account for a si...
Hard-to-predict branches depending on long-latency cache-misses have been recognized as a major perf...
There is a growing interest in the use of speculative multithreading to speed up the execution of se...
The execution time of programs that have large working sets is substantially increased by the overhe...
Efficient data supply to the processor is the one of the keys to achieve high performance. However, ...
Processor performance is directly impacted by the latency of the memory system. As processor core cy...
. Data speculation refers to the execution of an instruction before some logically preceding instruc...
One major restriction to the performance of out-of-order superscalar processors is the latency of lo...
Two orthogonal hardware techniques, table-based address prediction and early address calculation, fo...
Uno de los mayores retos que debe ser afrontado por los diseñadores de micro-procesadores es el de m...
Abstract — Recent works have proposed the use of prediction techniques to execute speculatively true...
Modern processors rely heavily on speculation to provide performance. Techniques such as branch pred...
While runahead execution is effective at parallelizing independent long-latency cache misses, it is ...
Branch prediction feeds a speculative execution processor core with instructions. Branch mispredicti...
In this correspondence, we propose design techniques that may significantly simplify the cache acces...
For many programs, especially integer codes, untolerated load instruction latencies account for a si...
Hard-to-predict branches depending on long-latency cache-misses have been recognized as a major perf...
There is a growing interest in the use of speculative multithreading to speed up the execution of se...
The execution time of programs that have large working sets is substantially increased by the overhe...
Efficient data supply to the processor is the one of the keys to achieve high performance. However, ...
Processor performance is directly impacted by the latency of the memory system. As processor core cy...