Value prediction improves instruction level parallelism in superscalar processors by breaking true data dependencies. Although this technique can significantly improve overall performance, most of the state-of-the-art value prediction approaches require high hardware cost, which is the main obstacle for its wide adoption in current processors. To tackle this issue, we revisit load value prediction as an efficient alternative to the classical approaches that predict all instructions. By speculating only on loads, the pressure over shared resources (e.g., the Physical Register File) and the predictor size can be substantially reduced (e.g., more than 90% reduction compared to recent works). We observe that existing value predictors cannot ach...
Recent trends regarding general purpose microprocessors have focused on Thread-Level Parallelism (TL...
[[abstract]]Value prediction can be used to break data dependency between instructions, ensuring sim...
To improve application performance, current processors rely on prediction-based hardware optimizatio...
To improve the performance and energy-efficiency of in-order processors, this paper proposes a novel...
The ever-increasing computational power of contemporary microprocessors reduces the execution time s...
The ever-increasing computational power of contemporary microprocessors reduces the execution time s...
One major restriction to the performance of out-of-order superscalar processors is the latency of lo...
International audienceEven in the multicore era, there is a continuous demand to increase the perfor...
International audienceUp to recently, it was considered that a performance-effe...
Even in the multicore era, making single cores faster is paramount to achieve high- performance comp...
While runahead execution is effective at parallelizing independent long-latency cache misses, it is ...
International audienceDedicating more silicon area to single thread perfor-mance will necessarily be...
International audienceIn this study we explore the performance limits of value prediction for unlimi...
International audienceIn this study we explore the performance limits of value prediction for small ...
A fait l'objet d'une publication à "High Performance Computer Architecture (HPCA) 2014" Lien : http:...
Recent trends regarding general purpose microprocessors have focused on Thread-Level Parallelism (TL...
[[abstract]]Value prediction can be used to break data dependency between instructions, ensuring sim...
To improve application performance, current processors rely on prediction-based hardware optimizatio...
To improve the performance and energy-efficiency of in-order processors, this paper proposes a novel...
The ever-increasing computational power of contemporary microprocessors reduces the execution time s...
The ever-increasing computational power of contemporary microprocessors reduces the execution time s...
One major restriction to the performance of out-of-order superscalar processors is the latency of lo...
International audienceEven in the multicore era, there is a continuous demand to increase the perfor...
International audienceUp to recently, it was considered that a performance-effe...
Even in the multicore era, making single cores faster is paramount to achieve high- performance comp...
While runahead execution is effective at parallelizing independent long-latency cache misses, it is ...
International audienceDedicating more silicon area to single thread perfor-mance will necessarily be...
International audienceIn this study we explore the performance limits of value prediction for unlimi...
International audienceIn this study we explore the performance limits of value prediction for small ...
A fait l'objet d'une publication à "High Performance Computer Architecture (HPCA) 2014" Lien : http:...
Recent trends regarding general purpose microprocessors have focused on Thread-Level Parallelism (TL...
[[abstract]]Value prediction can be used to break data dependency between instructions, ensuring sim...
To improve application performance, current processors rely on prediction-based hardware optimizatio...