Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has translated the programmer's original control structure directly into assembly code with conditional branch instructions. Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research. However, traditional branch handling techniques cannot significantly alter the program's inherent control structure. The advent of predication as a program control representation has enabled compilers t...
In this paper we evaluate the effects of guarded (or conditional, or predicated) execution on the pe...
Speculative execution has long been used as an approach to exploit instruction level parallelism acr...
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-...
Predicated execution is a promising architectural feature for exploiting instruction-level paralleli...
The performance of modern processors is increasingly de-pendent on their ability to execute multiple...
277 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.For many applications, specul...
185 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.The Partial Reverse If-Conver...
Architectural support for predicated execution has been proposed as a manner of attacking performanc...
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard...
Conventional speculative architectures use branch prediction to evaluate the most likely execution p...
textEven after decades of research in branch prediction, branch predictors still remain imperfect, w...
Partial redundancy elimination (PRE) is one of the most widespread optimizations in compilers. Howev...
The Explicitly Parallel Instruction Computing (EPIC) architecture has been put forth as a viable arc...
High performance architectures have always had to deal with the performance-limiting impact of branc...
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-pred...
In this paper we evaluate the effects of guarded (or conditional, or predicated) execution on the pe...
Speculative execution has long been used as an approach to exploit instruction level parallelism acr...
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-...
Predicated execution is a promising architectural feature for exploiting instruction-level paralleli...
The performance of modern processors is increasingly de-pendent on their ability to execute multiple...
277 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.For many applications, specul...
185 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.The Partial Reverse If-Conver...
Architectural support for predicated execution has been proposed as a manner of attacking performanc...
Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard...
Conventional speculative architectures use branch prediction to evaluate the most likely execution p...
textEven after decades of research in branch prediction, branch predictors still remain imperfect, w...
Partial redundancy elimination (PRE) is one of the most widespread optimizations in compilers. Howev...
The Explicitly Parallel Instruction Computing (EPIC) architecture has been put forth as a viable arc...
High performance architectures have always had to deal with the performance-limiting impact of branc...
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-pred...
In this paper we evaluate the effects of guarded (or conditional, or predicated) execution on the pe...
Speculative execution has long been used as an approach to exploit instruction level parallelism acr...
This paper proposes a new processor architecture for handling hard-to-predict branches, the diverge-...