Predicated execution has been used to reduce the number of branch mispredictions by eliminating hard-to-predict branches. However, the additional instruction overhead and additional data dependencies due to predicated execution sometimes offset the per-formance advantage of having fewer mispredictions. We propose a mechanism in which the compiler generates code that can be executed either as predicated code or non-predicated code (i.e., code with normal conditional branches). The hardware decides whether the predicated code or the non-predicated code is executed based on a run-time confidence estimation of the branch’s prediction. The code generated by the compiler is the same as pred-icated code, except the predicated conditional branches ...
A relativeA, small set of static instructions has significant leverage on program execution performa...
One of the key factors determining computer performance is the degree to which the implementation c...
Speculative execution has long been used as an approach to exploit instruction level parallelism acr...
277 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.For many applications, specul...
textEven after decades of research in branch prediction, branch predictors still remain imperfect, w...
Conventional speculative architectures use branch prediction to evaluate the most likely execution p...
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-pre...
Architectural support for predicated execution has been proposed as a manner of attacking performanc...
High performance architectures have always had to deal with the performance-limiting impact of branc...
Speculative execution of conditional branches has a high hardware cost, is limited by dynamic branc...
Predicated Execution can be used to alleviate the costs associated with frequently mispredicted bran...
Pipeline stalls due to branches represent one of the most significant impediments to realizing the p...
There is wide agreement that one of the most important impediments to the performance of current and...
The conditional branch has long been considered an expensive operation. The relative cost of conditi...
Predicated execution is a promising architectural feature for exploiting instruction-level paralleli...
A relativeA, small set of static instructions has significant leverage on program execution performa...
One of the key factors determining computer performance is the degree to which the implementation c...
Speculative execution has long been used as an approach to exploit instruction level parallelism acr...
277 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.For many applications, specul...
textEven after decades of research in branch prediction, branch predictors still remain imperfect, w...
Conventional speculative architectures use branch prediction to evaluate the most likely execution p...
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-pre...
Architectural support for predicated execution has been proposed as a manner of attacking performanc...
High performance architectures have always had to deal with the performance-limiting impact of branc...
Speculative execution of conditional branches has a high hardware cost, is limited by dynamic branc...
Predicated Execution can be used to alleviate the costs associated with frequently mispredicted bran...
Pipeline stalls due to branches represent one of the most significant impediments to realizing the p...
There is wide agreement that one of the most important impediments to the performance of current and...
The conditional branch has long been considered an expensive operation. The relative cost of conditi...
Predicated execution is a promising architectural feature for exploiting instruction-level paralleli...
A relativeA, small set of static instructions has significant leverage on program execution performa...
One of the key factors determining computer performance is the degree to which the implementation c...
Speculative execution has long been used as an approach to exploit instruction level parallelism acr...