Study of FPGA architecture using carbon nanotube field effect transistors (CNTFET)

This thesis is a study on designing, understanding and performance benchmarking of FPGA (Field Programmable Gate Array) logic cell, including both CMOS and CNTFET of 32nm node. Lately, both capacity and complexity of FPGA (field programmable gate array) devices are increasing swiftly. Also, it is common that battery powered embedded systems are equipped with field programmable gate array (FPGA) devices. Hence, the major issue here would be decreasing the consumption of power in FPGA (field programmable gate array) devices. As the size of fabrication FPGA (field programmable gate array) device shrinks, both dynamic power consumption and leakage power increases. Carbon nanotube (CNT) has substantial prospective to substitute silicon in the future prospects to diminish power consumption of FPGA (field programmable gate array) devices. Advanced electronic device technologies require a faster operation and smaller average power consumption, which are the most important parameters in very large scale integrated circuit design. The conventional CMOS (complementary metal-oxide semiconductor) is limited by the threshold voltage and subthreshold leakage problems despite a reduction in size. Therefore, CNT (Carbon nanotube) based technology replaces the former one as it has low leakage power, low current and power consumption, less static noise margin. In recent times, there has been remarkable progresses in Carbon nanotube (CNT) technology for nano electronic applications. CNTFET is the unique device that is anticipated to endure the transistor scalability while increasing the device performance. CNTFETs avoid most of the fundamental limitations and deal with several constraints that the existing silicon devices have. A simple model for FPGA cell is designed for evaluating power consumption and timing analysis of both models CMOS and CNTFET. The research work here in this thesis proposal is to design a logic cell in FPGA device with the Stanford 32nm CNTFET device model using Synopsys HSPICE. Performance characteristics, parameters of the design are observed and recorded through various simulations