Automatic application partitioning on FPGA/CPU systems based on detailed low-level information

Re configurable FPGA/CPU systems are widely described in literature as a viable processing solution for embedded and high end processing. One of the key issues of this kind of approach is the code partitioning between CPU and FPGA. The development of automatic partitioning tools allows to obtain optimized architecture without a specific knowledge of digital design. In this paper we present a framework which, starting from an ANSI C application code: (i) automatically identifies code fragments suitable for hardware implementation as specialized functional units (ii)for all these segments a synthesizable code is generated and sent to a synthesis tool, (iii) from the synthesis results, the segments to be implemented on FPGA are selected (iv) bitstream to configure the FPGA and modified C code to be executed on the CPU are generated. We applied this tool to standard benchmarks obtaining, with respect to state of the art, an improvement of up to 250% in the accuracy of performances estimation related to the selected segments of code. This leads to a more optimized code partitioning. © 2006 IEEE