Code Partitioning for Reconfigurable High-Performance Computing: A Case Study

In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the case study problem and SRC-6 MAPstation is used as the test platform. The overall execution time of the resulting implementation serves as the primary optimization criterion. The paper presents an overview of the SRC-6 architecture and programming tools and describes the case study problem, along with a timing analysis of its microprocessor-based implementation. Next, three code partitioning schemes are considered and their SRC-6 MAP implementations are described, including detailed timing analyses. The results are compared and conclusions are drawn as to what partitioning scheme characteristics contribute most to the reduction of the overall execution time of the algorithm. The results of this case study are applicable to a large class of problems that involve outsourcing computationally demanding tasks to a reconfigurable processor. 1