Simplified stimuli generation for scenario and assertion based verification

Simulation-based approaches that require to drive the design under verification (DUV) to specific conditions, like for example, scenario-based testing and dynamic assertion-based verification (ABV), cannot rely on generic coverage-driven stimuli generators. On the contrary, constraint-based generation must be adopted. In this context, among several solutions, the Universal Verification Methodology (UVM) and the SystemC Verification Library (SCV) represent the main alternatives. However, their powerfulness is paid in term of easiness of use. In fact, their application generally requires to write complex pieces of code to specify the constraints that must be satisfied by the stimuli generator to produce the desired sequences of values. More is the complexity of setting up an effective stimuli generator, more is the risk of failing to capture the right behaviour and/or having a longer verification time. To overcome these problems, the paper presents a framework and a corresponding language for the automatic generation of stimuli that requires to write intuitive and compact directives representing the desired constraints. The approach is independent from the language adopted for the DUV implementation and it works for both embedded hardware as well as embedded software