Creating Stimulus and Stimulating Creativity: Using the VMM Scenario Generator

The Verification Methodology Manual for SystemVerilog (VMM) standard library provides a scenario generator that can be built automatically to match any user-defined stimulus data class. This ready-to-run generator can then be customized to provide structured streams of randomized stimulus for a verification environment. This paper presents an introduction to simple customization of the VMM scenario generator, and then reports the experience with the management of more complex stimulus. It will also compare the tradeoffs between procedurally-generated scenarios and purely declarative, constraint-driven scenarios, and examine the potential of well-designed scenario generation to enhance effective re-use of verificatio