A pre-condition for any verification technique based on simulation is the generation of a high-quality set of stimuli that effectively and efficiently cover the whole state space of the Design Under Verification (DUV), including hard-to-reach corner cases. To cope with this necessity, several approaches for the automatic generation of stimuli have been proposed for both embedded software and high-level descriptions of hardware components. Most of these approaches use constraint solvers to generate the sequences of stimuli that trigger specific conditions, enabling the analysis of corner cases. However, the automatic identification of those conditions is still an open problem, especially for black-box designs. To fill in the gap, this paper ...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
As the complexity of current hardware systems rises, it is challenging to harden these systems again...
Functional verification continues to be one of the most time-consuming steps in the chip design cycl...
Abstract. The testing and formal verification of black box software components is a challenging doma...
Simulation-based approaches that require to drive the design under verification (DUV) to specific co...
Abstract—Simulation-based verification is still the most fre-quently used technique when complex des...
In the context of structural testing, automatic test-pattern generation (ATPG) may fail to provide s...
Despite the growing research effort in formal verification, constraint-based random simulation remai...
With the advance of SAT solvers, transforming a software program to a propositional formula has gene...
Digital integrated circuits play an important role in the development of new information technologie...
Due to high performance demand and varied usage requirements from computer systems, the complexity o...
Design verification has been a challenging problem due to the increasing complexity of modern system...
The goal of this thesis is to analyze and to find solutions of optimization problems derived from au...
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis....
Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (I...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
As the complexity of current hardware systems rises, it is challenging to harden these systems again...
Functional verification continues to be one of the most time-consuming steps in the chip design cycl...
Abstract. The testing and formal verification of black box software components is a challenging doma...
Simulation-based approaches that require to drive the design under verification (DUV) to specific co...
Abstract—Simulation-based verification is still the most fre-quently used technique when complex des...
In the context of structural testing, automatic test-pattern generation (ATPG) may fail to provide s...
Despite the growing research effort in formal verification, constraint-based random simulation remai...
With the advance of SAT solvers, transforming a software program to a propositional formula has gene...
Digital integrated circuits play an important role in the development of new information technologie...
Due to high performance demand and varied usage requirements from computer systems, the complexity o...
Design verification has been a challenging problem due to the increasing complexity of modern system...
The goal of this thesis is to analyze and to find solutions of optimization problems derived from au...
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis....
Modern Integrated Circuit (IC) design is characterized by a strong trend of Intellectual Property (I...
Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of comp...
As the complexity of current hardware systems rises, it is challenging to harden these systems again...
Functional verification continues to be one of the most time-consuming steps in the chip design cycl...