Novel n × n Bit-Serial Multiplier Architecture Optimized for Field Programmable Gate Arrays

Bit-serial multipliers have a variety of applications, from the implementation of neural networks to cryptography. The advantage of a bit-serial multiplier is its relatively small footprint, when implemented on a Field Programmable Gate Array (FPGA) device. Despite their apparent advantages, however, traditional bit-serial multipliers typically require a substantial overhead, in terms of component usage, which directly translates to a large area of the chip being reserved while many other resources are unused. This research addresses the possibility of an efficient two’s complement bit-serial multiplier (serial-serial multiplier) implementation that would minimize flip-flop and control set usage on an FPGA device, thereby potentially reducing the overall area of the circuit. Since the proposed architecture is modular, it functions as a “generic” definition that can be effortlessly implemented on an FPGA device for any number of bits