Efficient finite field digit-serial multiplier architecture for cryptography applications

BERTONI, GUIDO MARCO
BREVEGLIERI, LUCA ODDONE
FRAGNETO, PASQUALINA

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Publication date

January 2001

DOI

10.1109/DATE.2001.915150

Publisher

IEEE Computer Society Press

Abstract

Cryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated

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Efficient finite field digit-serial multiplier architecture for cryptography applications

Abstract

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Efficient finite field digit-serial multiplier architecture for cryptography applications

Abstract

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