FPGA Implementation of 16-bit Multipliers based upon Vedic Mathematic Approach

This paper proposes design and implementation of a 16-bit multiplier based upon Vedic mathematic<br />approach, where the design has been targeted to the Xilinx Field Programmable Gate Arrays (FPGAs) board, device<br />XC5VLX30. The approach is different from a number of approaches that have been used to realize multipliers. It<br />has been reported that previous algorithms such as Booth, Modified Booth, and Carry Save Multipliers only suitable<br />for improving speed or decreasing area utilization; therefore, those algorithms are not appropriate for designing<br />multipliers that are used for digital signal processing (DSP) applications. Moreover, they are not flexible to be<br />implemented on FPGAs or on a single chip using application specific integration circuits (ASICs). Vedic approach,<br />on the other hand, can be used to design multipliers with optimum speed and less area utilization. In addition, it is<br />reliable to be implemented on FPGAs or on a single chip. Behavioral and post-route simulation results prove that the<br />proposed multiplier shows better performance in terms of speed compared to the other reported multipliers when<br />being implemented on the FPGA. In terms of area utilization, better results are also obtained