The Design and Implementation of High-Speed Wireline Transceivers in CMOS Technology

在本論文中，我們研究了使用Duobinary, PAM4及NRZ此三種資料編碼方式之高速有線收發器於不同環境之下之表現與特性。論文中分析此三種收發器之理想特性並於最佳化設計之後，經由量測證明其結果。此三個收發器皆以台積電90奈米製程製作，三個收發器皆可透過10公分之FR4以及40公分之Rogers板材之傳輸線，以231-1之PRBS資料於20 Gb/s之資料傳輸速度下傳輸無誤。此之外，本論文提出一個針對液晶面版之時序控制器與列驅動器間傳輸所設計之高速且低功率輸出輸入介面電路。此電路使用台積電0.35微米製作，並可透過55公分之FR4板材，以以231-1之PRBS資料於1.2 Gb/s之資料傳輸速度下傳輸無誤。其傳輸端及接收端面積和為0.1mm2，於3.3伏特之電源供應下功率消耗為1.2毫安培。A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings are presented to evaluate their feasibility and to validate the performance prediction. The three transceivers have been tested thoroughly in Rogers and FR4 boards. Fabricated in 90-nm CMOS technology, all three transceivers achieve error-free operation with 20-Gb/s 231 − 1 PRBS data over 40-cm Rogers and 10-cm FR4 channels.nother one low-power high-speed I/O interfaced circuit targeting for data transmission between timing controller and column driver in TFT-LCD panel is proposed. The circuit uses a signal with very low amplitude and a high-speed transimpedance amplifier to reduce the power consumption while operating at a high data rate. The circuit is designed and fabricated in TSMC 0.35um CMOS technology. It can achieve error-free operation with 1.2-Gb/s 231-1 PRBS data over 55-cm FR4 channels. The power consumption is 4 mW under 3.3V supply and the core area is 0.1mm2.Chapter 1 Introduction 1.1 Motivation 1.2 Thesis Organization 2hapter 2 A 1.2-Gb/s Low-power I/O Circuit in 0.35um CMOS Technology For LCD-panel Data Transmission ..3.1 Introduction 3.2 Conventional LVDS panel System 5.3 Proposed Architecture and I/O Circuit 7.3.1 Point-to-point Architecture 7.3.2 Transmitter Design 8.3.3 Broadband Technique for Regulated-Cascode TIA 9.4 Experiment Results 14.5 Conclusion 16hapter 3 Introduction to Duobinary Signaling ..18.1 Duobinary Spectrum 18.2 Bandwidth Efficiency of Duobinary Signaling 20.3 Realization 21hapter 4 Comparison Among Duobinary, NRZ and PAM4 23hapter 5 Design of A 20Gb/s Duobinary Transceiver 26.1 Transmitter 26.1.1 Conventional and Proposed Decoder 26.1.2 Feedforword Equalizer 28.2 Receiver 29.2.1 Receiver Architecture 29.2.2 Comparator and V/I Converter 30hapter 6 Design of A 20Gb/s PAM4 and NRZ Transceiver 32.1 PAM4 Transmitter 32.2 PAM4 Receiver 33.3 NRZ Transceiver 35hapter 7 Experimental Results 36hapter 8 Conclusion 44ibliography 4