Modelling and Design of High-Speed Wireline Transceivers with Fully-Adaptive Equalization

High-speed wireline transceivers are analog/mixed-signal electronic circuits in charge of transferring massive amounts of data in a plethora of applications ranging from server racks, base stations of wireless networks, computing platforms and memory interfaces. Recently, automotive applications are emerging as a new field where high-speed data transfer is required to feed information to advanced driver-assistance systems responsible of increasing safety and possibly lead to autonomous vehicles. In order to design high-speed interfaces complying with automotive standards that demand wide operating conditions and high performance in harsh environments, a full understanding of such devices and of possible impairments is required. This work proposes simple, albeit accurate and computationally-efficient, probabilistic models capable of predicting the deleterious effect of inter-symbol interference caused by the transmissive medium, while replicating the behaviour of the transceiver's circuitry, so to provide a solid background to aid the system/circuit design. One of the major challenges in designing versatile high-speed interfaces is to cope with inter-symbol interference induced by unknown, high-loss channels. This can be achieved by employing fully-adaptive algorithms to automatically find the optimal settings for the equalizers to compensate the loss and distortion caused by the channel. A method to efficiently simulate such adaptive systems with the aforementioned statistical model is proposed and used to drive the design of an integrated 12 Gb/s PAM-2 transceiver in 28 nm planar CMOS technology, building on a previous chip developed at Infineon Technologies Villach, which was upgraded by modifying design and layout of specific, critical blocks that were identified following its laboratory characterisation. The new test chip was eventually fabricated and characterised to verify the implemented fully-adaptive algorithm when equalizing various channels with different characteristics. Having guaranteed adaptive equalization, as required in order to comply with modern automotive standards, the 16 Gb/s PAM-2 data rate that they target was considered next. This required to redesign the transmitter from scratch, shifting to a half-rate architecture and implementing circuits to guarantee efficient serialisation, output impedance matching and absence of duty cycle distortion on the 8 GHz clock to achieve the best performance. The aforementioned work on modelling, design and characterisation of fully-adaptive equalizers for high-speed wireline transceiver was then complemented with modelling activities related to jitter in clock- and data-recovery units, which are responsible for providing a clean and synchronised clock at the receive side to correctly sample the incoming data. Overall, the PhD work covered many of the most relevant concepts and building blocks of high-speed serial interfaces with modelling, design and laboratory characterisation. This allowed to gain a deep understanding of fundamental aspects such as inter-symbol interference and jitter, how they can be efficiently modelled and how they relate to and interact in the design of a fully-adaptive equalization algorithm and of a 16 Gb/s PAM-2 transmitter in 28 nm planar CMOS technology