FPGA Implementation of 100Mbps OFDM Transceiver

[[abstract]]本論文參考IEEE 802.16的系統規格，利用FPGA（Field Programmable Gate Array）發展板實現了一個有訊框架構的正交分頻多工（Orthogonal Frequency Division Multiplexing , OFDM）傳輸系統，量測訊號證明其系統資料傳輸速率最高可達100 Mbps。電路設計中使用了Xilinx Digital Clock Managers （DCMs）來解決複雜的時脈需求。本論文也設計了一個雙向的記憶體架構來組織訊框的結構，使電路面積能達到最精簡的使用效益。在重要的快速傅立葉轉換（Fast Fourier Transform , FFT）電路中採用256點FFT的Radix-2架構。本系統也採用一個12階的脈波整形濾波器來達到降低頻譜旁邊帶的要求。另外考慮未來的延伸設計需求，我們也加入Preamble設計，在符元序列中插入Preamble符元，未來將可直接在此平台上硬體實現通道估測、錯誤更正碼等技術。[[abstract]]An 100 Mbps orthogonal frequency division multiplexing (OFDM) transceiver has been verified and realized in the thesis by using field programmable gate array (FPGA). Preamble, plots, virtual carriers, and simple framer are also considered in the design so that the designed transceiver can be expanded in the future. In the circuit design, the Xilinx Digital Clock Managers（DCMs）are used to deal with the complicated timing. A radix-2 256 subcarriers of fast Fourier transform (FFT) was adopted as the modulator. A twelve-tap pulse shaping filter is used for side-lobe reduction. With this hardware platform, new developed technologies, such as channel estimation, detection, channel coding, carrier frequency offset recovery, etc., now can be verified and tested.[[note]]碩